Embodiments of the invention generally relate to processing design data for a semiconductor circuit, and more specifically, to a blockage area aware and placement and timing aware wire tagging for a layout of a semiconductor chip design.
Designing very large scale integration (VLSI) chips is a science and art at the same time. Modern tools help engineers with device placements and routing of signal lines. However, the process is far from being perfect and it cannot be automated completely. Currently, at the end of an implementation phase (also called Engineering Changed Order phase) of macros/rows/units/course/chips, there may have been an unrouteable netlist of routed netlists in which additional nets have to be implemented. In many times, these netlists have critical and uncritical nets or, need to cross blocked areas on the die. During the implementation process some of the nets may have been changed from critical to uncritical. But once changed they still use the same high wire resources needed at the beginning. However, one of the goals of very large scale integration (VLSI) design is to minimize required die areas and thus minimize power requirements. This is because additional buffers are not required or timing constraints may be met otherwise.
In such design processes, blockage areas require special attention because they have to be protected from inserting additional buffers into their middle. Therefore special attention is given to routing signal lines across or around such blockage areas. A result, at the end of a routing process, non-routed signal lines may still exist. Then, often a manual process starts to route the remaining signal lines that have not been routed automatically. This is a time-consuming, tedious, iterative and error-prone process which should be avoided. Additionally, experienced and thus expensive chip designers are required.